<!Doctype html>
<html>
<head>
	<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
	<meta name="viewport" content="width=device-width, initial-scale=1.0" />
	<title>4.1 Verilog 同步与异步 | 菜鸟教程</title>

  <meta name='robots' content='max-image-preview:large' />
<link rel='stylesheet' id='classic-theme-styles-css' href='../0/classic-themes.min.css?ver=6.2' type='text/css' media='all' />
<link rel="canonical" href="../w3cnote/verilog-sync.html" />
<meta name="keywords" content="4.1 Verilog 同步与异步">
<meta name="description" content="关键词： 同步，异步 由第 3 章可知，当触发器输入端的数据和触发器的时钟不相关时，很容易导致电路时序不满足。本章主要解决模块间可导致时序 violation 的异步问题。 关于异步与同步的定义，许多地方都有介绍，细节上也有所差异。本章主要的关注点是解决异步问题的方法，而不关心为什么会出现异步时钟，也不关心异步电路的具体结构，仅从异步时钟的时序结果去分析解决问题。  同步时钟 数字设计中，一般认为，频率相同或频率比为整数倍、且相位相同或..">
		
	<link rel="shortcut icon" href="https://static.runoob.com/images/favicon.ico">
	<link rel="stylesheet" href="../0/style.css?v=1.170" type="text/css" media="all" />	
	<link rel="stylesheet" href="../0/font-awesome.min.css" media="all" />	
  <!--[if gte IE 9]><!-->
  <script src=""></script>
  <!--<![endif]-->
  <!--[if lt IE 9]>
     <script src=""></script>
     <script src=""></script>
  <![endif]-->
  <link rel="apple-touch-icon" href="https://static.runoob.com/images/icon/mobile-icon.png"/>
  <meta name="apple-mobile-web-app-title" content="菜鸟教程">
</head>
<body>

<!--  头部 -->
<div class="container logo-search">

  <div class="col search row-search-mobile">
    <form action="index.php">
      <input class="placeholder" placeholder="搜索……" name="s" autocomplete="off">
      
    </form>
  </div>

  <div class="row">
    <div class="col logo">
      <h1><a href="../">菜鸟教程 -- 学的不仅是技术，更是梦想！</a></h1>
    </div>
        <div class="col right-list"> 
    <button class="btn btn-responsive-nav btn-inverse" data-toggle="collapse" data-target=".nav-main-collapse" id="pull" style=""> <i class="fa fa-navicon"></i> </button>
    </div>
        
    <div class="col search search-desktop last">
      <div class="search-input" >
      <form action="//www.runoob.com/" target="_blank">
        <input class="placeholder" id="s" name="s" placeholder="搜索……"  autocomplete="off" style="height: 44px;">
      </form>
      
      </div>
    </div>
  </div>
</div>



<!-- 导航栏 -->
<div class="container navigation">
    <div class="row">
        <div class="col nav">
            

                        <ul class="pc-nav" id="note-nav">
                <li><a href="../">首页</a></li>
                <li><a href="../w3cnote">笔记首页</a></li>
                <li><a href="../w3cnote/android-tutorial-intro.html" title="Android 基础入门教程">Android</a></li>
                <li><a href="../w3cnote/es6-tutorial.html" title="ES6 教程">ES6 教程</a></li>
                <li><a href="../w3cnote/ten-sorting-algorithm.html" title="排序算法">排序算法</a></li>
                <li><a href="../w3cnote/hadoop-tutorial.html" title="Hadoop 教程">Hadoop</a></li>
                <li><a href="../w3cnote/zookeeper-tutorial.html" title="Zookeeper 教程">Zookeeper</a></li>
                <li><a href="../w3cnote/verilog-tutorial.html" title="Verilog 教程">Verilog</a></li>
                <li><a href="../w3cnote_genre/code" title="编程技术">编程技术</a></li> 
                <li><a href="../w3cnote_genre/coderlife" title="程序员人生">程序员人生</a></li>
                
                <!--<li><a href="javascript:;" class="runoob-pop">登录</a></li>
                
                
                        <li>
                <a style="font-weight:bold;" href="../linux/linux-tutorial.html#yunserver" target="_blank" onclick="_hmt.push(['_trackEvent', 'aliyun', 'click', 'aliyun'])" title="kkb">云服务器</a>
                </li>
                <li><a href="http://gk.link/a/104mQ" target="_blank" style="font-weight: bold;"onclick="_hmt.push(['_trackEvent', '极客时间', 'click', 'jike'])" title="我的圈子">极客时间</a></li>
            
                
                <li><a target="_blank" href="../shoppinglist" rel="nofollow">知识店铺</a></li> 
        -->
            </ul>
                        
              
            <ul class="mobile-nav">
                <li><a href="../w3cnote">首页</a></li>
                <li><a href="../w3cnote_genre/android" target="_blank" title="Android 基础入门教程">Android</a></li>
                <li><a href="../w3cnote/es6-tutorial.html" target="_blank" title="ES6 教程">ES6</a></li>
                <li><a href="../w3cnote_genre/joke" target="_blank" title="程序员笑话">逗乐</a></li>
                
                <a href="javascript:void(0)" class="search-reveal">Search</a> 
            </ul>
            
        </div>
    </div>
</div>


<!--  内容  -->
<div class="container main">
	<div class="row">

		<!--  Android 基础入门教程 start  -->
	<div class="col left-column" style="display:none;">
		<div class="tab">Verilog 高级教程</div>
		<div class="sidebar-box gallery-list">
			<div class="design" id="leftcolumn">  
			</div> 
		</div> 
	</div>
	<!--  Android 基础入门教程 end  -->
		<div class="col middle-column big-middle-column">
	 			<div class="article">
			<div class="article-heading">
				<h2>4.1 Verilog 同步与异步</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog2" title="Verilog 教程高级篇" >Verilog 教程高级篇</a> </h3>
			</div>
			<div class="article-body note-body">
				<div class="article-intro">
					<h3>关键词： 同步，异步</h3>
<p>由第 3 章可知，当触发器输入端的数据和触发器的时钟不相关时，很容易导致电路时序不满足。本章主要解决模块间可导致时序 violation 的异步问题。</p><p>
关于异步与同步的定义，许多地方都有介绍，细节上也有所差异。本章主要的关注点是解决异步问题的方法，而不关心为什么会出现异步时钟，也不关心异步电路的具体结构，仅从异步时钟的时序结果去分析解决问题。</p><hr>
<h2>
同步时钟</h2><p>
数字设计中，一般认为，频率相同或频率比为整数倍、且相位相同或相位差固定的两个时钟为同步时钟。</p><p>
或者理解为，时钟同源且频率比为整数倍的两个时钟为同步时钟。其实，时钟同源，就保证了时钟相位差的固定性。具体可以分类如下：</p>

<h3>同源同频同相位</h3><p>
此类时钟频率和相位均相同，是同步的。时钟间数据传输只要满足正常的建立时间和保持时间即可，不需要特殊的同步设计。</p>
<h3>同源同频不同相位</h3><p>
两个时钟同频但不同相位时，只要相位差保持固定，也可以认为是同步的。因为只要控制两个时钟间传输的数据延迟在合理范围内，就不会导致时序问题。而且，固定的时钟延迟也可以在版图级网表中修复。</p><p>
固定的相位差可以理解为同源时钟下两个时钟因路径不同而导致的偏移。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-sync-1.png"></p>
<h3>同源不同频但存在整数倍分频比</h3><p>
此类情况下，一个时钟往往是另一个时钟的分频，即便存在相位差也是固定的。</p><p>
当单 bit 信号从慢时钟域传递到快时钟域时，因为同源，只要满足建立时间和保持时间，快时钟域总会采集到从慢时钟域传递来的信号。</p><p>
如下图所示，clk2 上升沿总能采集从 clk1 域来的信号 sig1，且采集到的信号 sig2 高电平持续周期也是两个时钟的频率比，即 2 个周期。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-sync-2.png"></p>
<p>如果要求 clk2 域的信号 sig2 只需要持续一个时钟周期，则需要对 sig1 进行上升沿检测。</p><p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
同步信号间的上升沿检测程序 Verilog 描述如下。<span style="color: #5D478B;">&lt;/</span>p<span style="color: #5D478B;">&gt;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;sig2_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk2 <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> sig2_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">2'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">else</span> &nbsp; &nbsp; &nbsp; sig2_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #9F79EE;">&#123;</span>sig2_r<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">,</span> sig1<span style="color: #9F79EE;">&#125;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> sig2 <span style="color: #5D478B;">=</span> sig2_r<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">&amp;&amp;</span> <span style="color: #5D478B;">!</span>sig2_r<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">;</span><br />
</div></div>
<p>仿真结婚下图所示。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-sync-3.png"></p>

<p>当单 bit 信号从快时钟域传递到慢时钟域时，只要慢时钟域能安全采集到从快时钟域传递来的信号，就不存在异步问题。因为两个时钟是同源的。如下图 sig1 到 sig2 的传输。</p><p>
但是如果快时钟域信号过窄，慢时钟域可能会漏掉该信号，如下图 sig11 到 sig22 的传输。此时就需要对快时钟域的窄脉冲信号进行展宽。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-sync-4.png"></p>
<p>当两个时钟频率比相对较小时，可以在快时钟域采用对信号延迟的方法进行展宽；</p><p>
当两个时钟频率比相差较大时，可在快时钟域采用计数的方法来延长单 bit 信号有效的时间。</p><p>
利用延迟来展宽窄脉冲信号的方法 Verilog 描述如下。因为 clk1 与 clk2 的频率比为 2，只需要在 clk2 时钟域延迟 2 拍即可。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;sig11_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk1 <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> sig11_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">2'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">else</span> &nbsp; &nbsp; &nbsp; sig11_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #9F79EE;">&#123;</span>sig11_r<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">,</span> sig11<span style="color: #9F79EE;">&#125;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;sig22_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk2 <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp;sig22_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;sig22_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #5D478B;">|</span>sig11_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> sig22 <span style="color: #5D478B;">=</span> sig22_r <span style="color: #5D478B;">;</span><br />
</div></div><p>
此时，快时钟域的信号被延迟 2 拍，总会被慢时钟域采集到，如下图所示。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-sync-5.png"></p>
<p>
总之，同源且频率比为整数倍关系时，可以理解为这两个时钟是同步的，不需要特殊的同步处理。下面，简单介绍下异步时钟的情况。</p>
<hr><h2>
异步时钟</h2><p>
工作在异步时钟下的两个模块进行数据交互时，由于时钟相位关系不可控制，很容易导致建立时间和保持时间 violation。以下 3 种情况下的时钟可以认为是异步的。</p>

<h3>不同源</h3><p>
由两个不同的时钟源产生的两个时钟是异步的，这是最常见的异步时钟。即便两个时钟频率相同，但是也不能保证每次上电后两者的相位或相位差是相同的，所以信号间的传输与时钟关系也是不确定的。</p>
<h3>同源但频率比不是整数倍</h3><p>
此时两个时钟间相位差也可能会有多个，例如同源的 7MHz 时钟和 3MHz 时钟，他们之间也会出现多个相位差，时序也难以控制。一般情况下也需要当异步时钟处理。</p>
<h3>同源虽频率比为整数倍但不满足时序要求</h3>
<p>前面介绍同步问题时有说明，当信号从快时钟域传递到慢时钟域时，只要慢时钟域能安全采集到从快时钟域传来的信号，就不存在异步问题。但如果信号在快时钟域翻转速率过快，慢时钟域可能不会安全的采集到从快时钟域传来的信号，这也可以认为是异步问题。</p>
<p>一般来说，慢时钟域时序约束较为宽松，快时钟域较为严格。</p><p>
如下图，快时钟域信号在慢时钟域上升沿前翻转了 2 次。此时，慢时钟域会漏掉部分数据。而且，数据的快速变化也可能导致 timing violation。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-sync-6.png"></p>
<p>这里只简单介绍下异步时钟的分类情况，异步问题的解决方法请参考后面的章节。</p>
<h3>本章节源码下载</h3><p>
<a class="download" href="../wp-content/uploads/2021/05/v4.1_sync.zip">Download</a>   </p>				</div>
			</div>
			<div class="previous-next-links">
			<div class="previous-design-link">← <a href="../w3cnote/verilog2-sdf.html" rel="prev"> 3.5 Verilog 延迟反标注</a> </div>
			<div class="next-design-link"><a href="../w3cnote/verilog2-slow2fast.html" rel="next"> 4.2 Verilog 跨时钟域传输：慢到快</a> →</div>
			</div>
						<div class="article-heading-ad" id="w3cnote-ad728">
			<script async src=""></script>
			<!-- 移动版 自动调整 -->
			<ins class="adsbygoogle"
			     style="display:inline-block;min-width:300px;max-width:970px;width:100%;height:90px"
			     data-ad-client="ca-pub-5751451760833794"
			     data-ad-slot="1691338467"
			     data-ad-format="horizontal"></ins>
			<script>
			(adsbygoogle = window.adsbygoogle || []).push({});
			</script>
			</div>
			<style>
@media screen and (max-width: 768px) {
	#w3cnote-ad728 {
		display: none;
	}
}
p.note-author {
    border-bottom: 1px solid #ddd;
    font-size: 18px;
    font-weight: bold;
    color: #78a15a;
    padding-bottom: 2px;
    margin-bottom: 4px;
}
</style>
<script>
var aid = 23714;
</script>
	</div>
		
	</div>
	<div class="listcol last right-column">

	<script type="text/javascript">
jQuery(document).ready(function ($){
	var total = $(".membership li").length;
	var left_list = '';
	href = window.location.href;
	
	$(".membership li").each(function(index, value){

		left_list += $(this).html();

		cur_href = $(this).find("a").attr("href");
		cur_obj = $(this);
		
		if(href.match(cur_href) != null) {
			if(index==0) {
				$(".previous-design-link").hide();
			}
			if(index==(total-1)) {
				$(".next-design-link").hide();
			}
			prev_href = cur_obj.prev("li").find("a").attr("href");
			prev_title = cur_obj.prev("li").find("a").attr("title");

			next_href = cur_obj.next("li").find("a").attr("href");
			next_title = cur_obj.next("li").find("a").attr("title");
			if(prev_title) {
				$(".previous-design-link a").attr("href", prev_href);
				$(".previous-design-link a").attr("title", prev_title);
				$(".previous-design-link a").text(prev_title);
			} else {
				$(".previous-design-link").html("");
			}

			if(next_title) {
				$(".next-design-link a").attr("href", next_href);
				$(".next-design-link a").attr("title", next_title);
				$(".next-design-link a").text(next_title);
			} else {
				$(".next-design-link").html("");
			}
		}
	});

	$("#leftcolumn").html(left_list);
});
	</script>
	<div class="sidebar-box cate-list">
	<div class="sidebar-box recommend-here list-link">
	<a href="javascript:void(0);">Verilog 高级教程</a>	</div>
	
	<ul class="membership">
		
	<li><a target="_top" data-id="23639" title="0.1 数字逻辑设计" href="../w3cnote/verilog2-tutorial.html" >0.1 数字逻辑设计</a></li>
	
		
	<li><a target="_top" data-id="23641" title="0.2 Verilog 编码风格" href="../w3cnote/verilog2-codestyle.html" >0.2 Verilog 编码风格</a></li>
	
		
	<li><a target="_top" data-id="23644" title="0.3 Verilog 代码规范" href="../w3cnote/verilog2-codeguide.html" >0.3 Verilog 代码规范</a></li>
	
		
	<li><a target="_top" data-id="23645" title="1.1 Verilog 门的类型" href="../w3cnote/verilog2-gate.html" >1.1 Verilog 门的类型</a></li>
	
		
	<li><a target="_top" data-id="23648" title="1.2 Verilog 开关级建模" href="../w3cnote/verilog2-level-modeling.html" >1.2 Verilog 开关级建模</a></li>
	
		
	<li><a target="_top" data-id="23656" title="1.3 Verilog 门延迟" href="../w3cnote/verilog2-gate-delay.html" >1.3 Verilog 门延迟</a></li>
	
		
	<li><a target="_top" data-id="23673" title="2.1 Verilog UDP 基础知识" href="../w3cnote/verilog2-udp.html" >2.1 Verilog UDP 基础知识</a></li>
	
		
	<li><a target="_top" data-id="23674" title="2.2 Verilog 组合逻辑 UDP" href="../w3cnote/verilog2-udp-logic.html" >2.2 Verilog 组合逻辑 UDP</a></li>
	
		
	<li><a target="_top" data-id="23677" title="2.3 Verilog 时序逻辑 UDP" href="../w3cnote/verilog2-udp-timing.html" >2.3 Verilog 时序逻辑 UDP</a></li>
	
		
	<li><a target="_top" data-id="23685" title="3.1 Verilog 延迟模型" href="../w3cnote/verilog2-delay-type.html" >3.1 Verilog 延迟模型</a></li>
	
		
	<li><a target="_top" data-id="23690" title="3.2 Verilog specify 块语句" href="../w3cnote/verilog2-specify.html" >3.2 Verilog specify 块语句</a></li>
	
		
	<li><a target="_top" data-id="23692" title="3.3 Verilog 建立时间和保持时间" href="../w3cnote/verilog2-setup-hold-time.html" >3.3 Verilog 建立时间和保持时间</a></li>
	
		
	<li><a target="_top" data-id="23701" title="3.4 Verilog 时序检查" href="../w3cnote/verilog2-timing-check.html" >3.4 Verilog 时序检查</a></li>
	
		
	<li><a target="_top" data-id="23708" title="3.5 Verilog 延迟反标注" href="../w3cnote/verilog2-sdf.html" >3.5 Verilog 延迟反标注</a></li>
	
		<li>
	4.1 Verilog 同步与异步	</li>
	
		
	<li><a target="_top" data-id="23725" title="4.2 Verilog 跨时钟域传输：慢到快" href="../w3cnote/verilog2-slow2fast.html" >4.2 Verilog 跨时钟域传输：慢到快</a></li>
	
		
	<li><a target="_top" data-id="23729" title="4.3 Verilog 跨时钟域传输：快到慢" href="../w3cnote/verilog2-fast2slow.html" >4.3 Verilog 跨时钟域传输：快到慢</a></li>
	
		
	<li><a target="_top" data-id="23731" title="4.4 Verilog FIFO 设计" href="../w3cnote/verilog2-fifo.html" >4.4 Verilog FIFO 设计</a></li>
	
		
	<li><a target="_top" data-id="23739" title="5.1 Verilog 复位简介" href="../w3cnote/verilog2-reset.html" >5.1 Verilog 复位简介</a></li>
	
		
	<li><a target="_top" data-id="23743" title="5.2 Verilog 时钟简介" href="../w3cnote/verilog2-clock.html" >5.2 Verilog 时钟简介</a></li>
	
		
	<li><a target="_top" data-id="23757" title="5.3 Verilog 时钟分频" href="../w3cnote/verilog2-clock-division.html" >5.3 Verilog 时钟分频</a></li>
	
		
	<li><a target="_top" data-id="23768" title="5.4 Verilog 时钟切换" href="../w3cnote/verilog2-clock-switch.html" >5.4 Verilog 时钟切换</a></li>
	
		
	<li><a target="_top" data-id="23779" title="6.1 Verilog 低功耗简介" href="../w3cnote/verilog2-low-power.html" >6.1 Verilog 低功耗简介</a></li>
	
		
	<li><a target="_top" data-id="23788" title="6.2 Verilog 系统级低功耗设计" href="../w3cnote/verilog2-lower-power-design.html" >6.2 Verilog 系统级低功耗设计</a></li>
	
		
	<li><a target="_top" data-id="23792" title="6.3 Verilog  RTL 级低功耗设计（上）" href="../w3cnote/verilog2-rtl-low-power-design-1.html" >6.3 Verilog  RTL 级低功耗设计（上）</a></li>
	
		
	<li><a target="_top" data-id="23796" title="6.4 Verilog RTL 级低功耗设计（下）" href="../w3cnote/verilog2-rtl-low-power-design-2.html" >6.4 Verilog RTL 级低功耗设计（下）</a></li>
	
		
	<li><a target="_top" data-id="23806" title="7.1 Verilog 显示任务" href="../w3cnote/verilog2-display.html" >7.1 Verilog 显示任务</a></li>
	
		
	<li><a target="_top" data-id="23813" title="7.2 Verilog 文件操作" href="../w3cnote/verilog2-file.html" >7.2 Verilog 文件操作</a></li>
	
		
	<li><a target="_top" data-id="23825" title="7.3 Verilog 随机数及概率分布" href="../w3cnote/verilog2-random.html" >7.3 Verilog 随机数及概率分布</a></li>
	
		
	<li><a target="_top" data-id="23847" title="7.4 Verilog 实数整数转换" href="../w3cnote/verilog2-real2int.html" >7.4 Verilog 实数整数转换</a></li>
	
		
	<li><a target="_top" data-id="23851" title="7.5 Verilog 其他系统任务" href="../w3cnote/verilog2-other-task.html" >7.5 Verilog 其他系统任务</a></li>
	
		
	<li><a target="_top" data-id="23862" title="8.1 Verilog  PLI 简介" href="../w3cnote/verilog2-pli-intro.html" >8.1 Verilog  PLI 简介</a></li>
	
		
	<li><a target="_top" data-id="23865" title="8.2 Verilog TF 子程序" href="../w3cnote/verilog2-tf.html" >8.2 Verilog TF 子程序</a></li>
	
		
	<li><a target="_top" data-id="23869" title="8.3 Verilog TF 子程序列表" href="../w3cnote/verilog2-tf-sub.html" >8.3 Verilog TF 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23870" title="8.4 Verilog ACC 子程序" href="../w3cnote/verilog2-acc.html" >8.4 Verilog ACC 子程序</a></li>
	
		
	<li><a target="_top" data-id="23872" title="8.5 Verilog ACC 子程序列表" href="../w3cnote/verilog2-acc-sub.html" >8.5 Verilog ACC 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23876" title="9.1 Verilog 逻辑综合" href="../w3cnote/verilog2-logic-sumarry.html" >9.1 Verilog 逻辑综合</a></li>
	
		
	<li><a target="_top" data-id="23882" title="9.2 Verilog 可综合性设计" href="../w3cnote/verilog2-integrated-design.html" >9.2 Verilog 可综合性设计</a></li>
	
	</ul></div>	</div>
</div>


<!-- 底部 -->
<div id="footer" class="mar-t50">
   <div class="runoob-block">
    <div class="runoob cf">
     <dl>
      <dt>
       在线实例
      </dt>
      <dd>
       &middot;<a target="_blank" href="../html/html-examples.html">HTML 实例</a>
      </dd>
      <dd>
       &middot;<a target="_blank" href="../css/css-examples.html">CSS 实例</a>
      </dd>
      <dd>
       &middot;<a target="_blank" href="../js/js-examples.html">JavaScript 实例</a>
      </dd>
      <dd>
       &middot;<a target="_blank" href="../ajx/ajax-examples.html">Ajax 实例</a>
      </dd>
       <dd>
       &middot;<a target="_blank" href="../jquery/jquery-examples.html">jQuery 实例</a>
      </dd>
      <dd>
       &middot;<a target="_blank" href="../xml/xml-examples.html">XML 实例</a>
      </dd>
      <dd>
       &middot;<a target="_blank" href="../java/java-examples.html">Java 实例</a>
      </dd>
     
     </dl>
     <dl>
      <dt>
      字符集&工具
      </dt>
      <dd>
       &middot; <a target="_blank" href="../charsets/html-charsets.html">HTML 字符集设置</a>
      </dd>
      <dd>
       &middot; <a target="_blank" href="../tags/html-ascii.html">HTML ASCII 字符集</a>
      </dd>
     <dd>
       &middot; <a target="_blank" href="https://c.runoob.com/front-end/6939/">JS 混淆/加密</a>
      </dd> 
      <dd>
       &middot; <a target="_blank" href="https://c.runoob.com/front-end/6232/">PNG/JPEG 图片压缩</a>
      </dd>
      <dd>
       &middot; <a target="_blank" href="../tags/html-colorpicker.html">HTML 拾色器</a>
      </dd>
      <dd>
       &middot; <a target="_blank" href="..//c.runoob.com/front-end/53">JSON 格式化工具</a>
      </dd>
      <dd>
       &middot; <a target="_blank" href="..//c.runoob.com/front-end/6680/">随机数生成器</a>
      </dd>
     </dl>
     <dl>
      <dt>
       最新更新
      </dt>
                   <dd>
       &middot;
      <a href="../matplotlib/matplotlib-imread.html" title="Matplotlib imread() 方法">Matplotlib imre...</a>
      </dd>
              <dd>
       &middot;
      <a href="../matplotlib/matplotlib-imsave.html" title="Matplotlib imsave() 方法">Matplotlib imsa...</a>
      </dd>
              <dd>
       &middot;
      <a href="../matplotlib/matplotlib-imshow.html" title="Matplotlib imshow() 方法">Matplotlib imsh...</a>
      </dd>
              <dd>
       &middot;
      <a href="../matplotlib/matplotlib-hist.html" title="Matplotlib 直方图">Matplotlib 直方图</a>
      </dd>
              <dd>
       &middot;
      <a href="../python3/python-func-object.html" title="Python object() 函数">Python object()...</a>
      </dd>
              <dd>
       &middot;
      <a href="../python3/python-ai-draw.html" title="Python AI 绘画">Python AI 绘画</a>
      </dd>
              <dd>
       &middot;
      <a href="../w3cnote/cursor-editor.html" title="神辅助 Cursor 编辑器，加入 GPT-4 让编码更轻松！">神辅助 Cursor ...</a>
      </dd>
             </dl>
     <dl>
      <dt>
       站点信息
      </dt>
      <dd>
       &middot;
       <a target="_blank" href="mailto:admin@runoob.com" rel="external nofollow">意见反馈</a>
       </dd>
      <dd>
       &middot;
      <a target="_blank" href="../disclaimer">免责声明</a>
       </dd>
      <dd>
       &middot;
       <a target="_blank" href="../aboutus">关于我们</a>
       </dd>
      <dd>
       &middot;
      <a target="_blank" href="../archives">文章归档</a>
      </dd>
    
     </dl>
    
     <div class="search-share">
      <div class="app-download">
        <div>
         <strong>关注微信</strong>
        </div>
      </div>
      <div class="share">
      <img width="128" height="128" src="/wp-content/themes/runoob/assets/images/qrcode.png" />
       </div>
     </div>
     
    </div>
   </div>
   <div class="w-1000 copyright">
     Copyright &copy; 2013-2023    <strong><a href="../" target="_blank">菜鸟教程</a></strong>&nbsp;
    <strong><a href="../" target="_blank">runoob.com</a></strong> All Rights Reserved. 备案号：<a target="_blank" rel="nofollow" href="https://beian.miit.gov.cn/">闽ICP备15012807号-1</a>
   </div>
  </div>
  <div class="fixed-btn">
    <a class="go-top" href="javascript:void(0)" title="返回顶部"> <i class="fa fa-angle-up"></i></a>
    <a class="qrcode"  href="javascript:void(0)" title="关注我们"><i class="fa fa-qrcode"></i></a>
    <a class="writer" style="display:none" href="javascript:void(0)"   title="标记/收藏"><i class="fa fa-star" aria-hidden="true"></i></a>
    <!-- qrcode modal -->
    <div id="bottom-qrcode" class="modal panel-modal hide fade in">
      <h4>微信关注</h4>
      <div class="panel-body"><img alt="微信关注" width="128" height="128" src="/wp-content/themes/runoob/assets/images/qrcode.png"></div> 
    </div>
  </div>

 <div style="display:none;">
<script async src="https://www.googletagmanager.com/gtag/js?id=UA-84264393-2"></script>
<script>
  window.dataLayer = window.dataLayer || [];
  function gtag(){dataLayer.push(arguments);}
  gtag('js', new Date());

  gtag('config', 'UA-84264393-2');
</script>
<script>
var _hmt = _hmt || [];
(function() {
  var hm = document.createElement("script");
  hm.src = "https://hm.baidu.com/hm.js?3eec0b7da6548cf07db3bc477ea905ee";
  var s = document.getElementsByTagName("script")[0]; 
  s.parentNode.insertBefore(hm, s);
})();
</script>

</div>
<script>
window.jsui={
    www: 'https://www.runoob.com',
    uri: 'https://www.runoob.com/wp-content/themes/runoob'
};
</script>

<script src=""></script>
<script src=""></script>

</body>
</html>